I'm sure many of you have seen the new SNES PowerPak. After it was released, I sort of lost interest in some of the stuff I wanted to work on (SDRAM interface, menu system, etc) since none of it was really "new" anymore. Plus my job has been pretty intellectually fulfilling, so I hadn't spent much time on side projects.
Well, we had a week off for Christmas so I finally got bored enough to sit down and work on some things. I finished bringing up the USB port on my prototype, so I can load the FPGA core over usb. It enumerates as a HID device (no drivers, woooo!), and I use a little custom app to transfer the core file. For this FPGA, the cores end up being roughly 277kb max, and take about 4 seconds or so to fully transfer (64kbyte/sec, max speed for HID).
you can see the usb cable sticking out of the side of the prototype:
I also looked into some soft-cpu options to try and understand if it would be feasible to emulate the DSP chip in software on the cart. My main concerns were:
- Ability to fit on the inexpensive 250k gate spartan 3e (turns out the biggest issue is probably the amount of on-chip BRAM)
- Availability of a reasonable C toolchain (avoiding asm if possible.. the project is hard enough as it is)
Since we only have about 27kbyte of BRAM to work with, some of which the soft-cpu will have to dedicate for processing, I was concerned about how much code gets produced from a small C app with the given toolchain.
I played around with the Zylin ZPU. Which has a gcc toolchain, and if you use the larger implementation of the processor, the binaries are very small, merely 54 bytes (demo code) for looping to wait on a register, and then setting another register.
I think that it should be pretty feasible to emulate the DSP with this method. As for the other special chips... I'm not sure. For things like DMA engines, surely it will need a hardware implementation. I am assuming that there are enough hardware parts that it might make sense to just do everything in hardware.
I wish I knew a good book on doing custom CPUs with VHDL/Verilog. I can probably make it up as I go along, but it would be nice to have some background from a knowledgeable source.
